مرکز اطلاعات علمی Scientific Information Database (SID) - Trusted Source for Research and Academic Resources

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Information Journal Paper

Title

Power Reduction of the Low Offset Dynamic Comparator with Novel Techniques

Pages

  15-20

Abstract

 In this paper, dynamic comparators structure, by employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters, have been presented. The proposed comparators have low consumption thanks to power reduction methods. They have the ability for adjusting the offset. The comparators consume 14. 3 and 24 μ W at 100 MHz, which is equal to 3. 7 and 11. 8 fJ. The comparators are designed and simulated in 180 nm CMOS. Layouts occupy 210 and 240 μ m2, respectively.

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    • Cite

    APA: Copy

    Yousefi, Mousa, & MONFAREDI, KHALIL. (2019). Power Reduction of the Low Offset Dynamic Comparator with Novel Techniques. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, 13(2), 15-20. SID. https://sid.ir/paper/723742/en

    Vancouver: Copy

    Yousefi Mousa, MONFAREDI KHALIL. Power Reduction of the Low Offset Dynamic Comparator with Novel Techniques. MAJLESI JOURNAL OF ELECTRICAL ENGINEERING[Internet]. 2019;13(2):15-20. Available from: https://sid.ir/paper/723742/en

    IEEE: Copy

    Mousa Yousefi, and KHALIL MONFAREDI, “Power Reduction of the Low Offset Dynamic Comparator with Novel Techniques,” MAJLESI JOURNAL OF ELECTRICAL ENGINEERING, vol. 13, no. 2, pp. 15–20, 2019, [Online]. Available: https://sid.ir/paper/723742/en

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