A New Circuit Scheme for Wide Dynamic Circuits

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Asyaei M.

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Journal Paper

Paper Information

Journal: INTERNATIONAL JOURNAL OF ENGINEERING Year:2018 | Volume:31 | Issue:5 (TRANSACTIONS B: Applications) Page(s): 699-704

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Information Journal Paper

Title

A New Circuit Scheme for Wide Dynamic Circuits

Author(s)

Asyaei M. | Issue Writer Certificate

Keywords

Dynamic circuit

Keeper

Leakage current

Noise immunity

Wide fan-in gates

Abstract

In this paper, a new circuit scheme is proposed to reduce the power consumption of Dynamic circuits. In the proposed circuit, an NMOS Keeper transistor is used to maintain the voltage level in the output node against charge sharing, Leakage current and noise sources. Using the proposed Keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of Wide fan-in gates. Furthermore, the subthreshold Leakage current is decreased by using the footer transistor in diode configuration and consequently, the Noise immunity is increased in the proposed circuit. Simulation results of wide fan-in OR gates in 90nm CMOS technology demonstrate 48% power reduction and 1. 65× noise-immunity improvement at the same delay compared to the conventional Dynamic circuit for 32-bit OR gates.

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APA: Copy

Asyaei, M.. (2018). A New Circuit Scheme for Wide Dynamic Circuits. INTERNATIONAL JOURNAL OF ENGINEERING, 31(5 (TRANSACTIONS B: Applications)), 699-704. SID. https://sid.ir/paper/730350/en

Vancouver: Copy

Asyaei M.. A New Circuit Scheme for Wide Dynamic Circuits. INTERNATIONAL JOURNAL OF ENGINEERING[Internet]. 2018;31(5 (TRANSACTIONS B: Applications)):699-704. Available from: https://sid.ir/paper/730350/en

IEEE: Copy

M. Asyaei, “A New Circuit Scheme for Wide Dynamic Circuits,” INTERNATIONAL JOURNAL OF ENGINEERING, vol. 31, no. 5 (TRANSACTIONS B: Applications), pp. 699–704, 2018, [Online]. Available: https://sid.ir/paper/730350/en

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