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Information Journal Paper

Title

A New Low-Power Schema for DA-based FIR filters front-end shift-register arrays utilizing statistical properties of massive inputs

Author(s)

 Ghamkhari S.F. | ghaznavi Ghooshchi Mohammad Bagher | Issue Writer Certificate 

Pages

  101-113

Abstract

 The general model for hardware accelerators and stream processors in the area of video, image or audio processing is comprised of two major parts of very large array of shift registers and arithmetic elements. A common example of digital signal processing units that fit the general model of data stream processors is the DA-based FIR, which uses add and shifts to perform multiply operations instead of high-cost multipliers. The shift registers are the major dynamic power consumer of data stream processors and FIR Filters, thus reducing the power consumption of the storage elements can contribute to energy efficiency of the whole system. On the other hand, the study of statistical properties can play an important role in the design and improvement of basic circuit parameters such as power consumption and efficiency. For example, transition density (TD) is one of the main parameters in dynamic (or switching) power consumption. By examining the TDs at the inputs of the data stream processors; where the data is a set of images selected from a database, it is shown that the TDs are less than 0. 5 in 55% of the inputs. Due to the sparsity of the evaluated signals, a low-power flip flop is designed in 65nm technology by applying clock-gating and Multi-Vdd methods, which is suitable for use in shift registers. Simultaneous use of two methods of clock-gating and Multi-Vdd in the 8×5 shift register array can achieve an improvement between 26 to 86% in dynamic and 84% improvement in static power consumption.

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    • Cite

    APA: Copy

    Ghamkhari, S.F., & ghaznavi Ghooshchi, Mohammad Bagher. (2020). A New Low-Power Schema for DA-based FIR filters front-end shift-register arrays utilizing statistical properties of massive inputs. ELECTRONIC INDUSTRIES, 11(3 ), 101-113. SID. https://sid.ir/paper/957341/en

    Vancouver: Copy

    Ghamkhari S.F., ghaznavi Ghooshchi Mohammad Bagher. A New Low-Power Schema for DA-based FIR filters front-end shift-register arrays utilizing statistical properties of massive inputs. ELECTRONIC INDUSTRIES[Internet]. 2020;11(3 ):101-113. Available from: https://sid.ir/paper/957341/en

    IEEE: Copy

    S.F. Ghamkhari, and Mohammad Bagher ghaznavi Ghooshchi, “A New Low-Power Schema for DA-based FIR filters front-end shift-register arrays utilizing statistical properties of massive inputs,” ELECTRONIC INDUSTRIES, vol. 11, no. 3 , pp. 101–113, 2020, [Online]. Available: https://sid.ir/paper/957341/en

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