ELECTRONIC INDUSTRIES
Year:2020 | Volume:11 | Issue:3|Papers Count:10

In this paper a rail-to-rail time-domain CMOS winner take all (WTA) circuit is proposed. To convert the analog voltage to a delay time a voltage controlled delay line is employed. In order to implement a full range time domain winner take all, a linear rail-to-rail delay element is employed. A positive feedback loop is utilized to reduce the decision time. Employing a linear rail-to-rail delay element, improves the precision and dynamic range of the entire winner take all circuit. In addition, the proposed circuit is employed a new phase detector to reduce transistors have been utilized in the circuit and decrease the parasitic elements of VCDLs. As a result the proposed circuit is designed to operate in subthreshold region to 0. 3V. Based on the proposed structure, a 3-input WTA circuit has been designed and simulated in a 0. 18um CMOS technology with a 1V supply voltage. The simulated results confirm that the power consumption of the presented winner take all circuit is 0. 72uW at 10MHz clock frequency. The simulation results show the Figure of Merit of 2. 4uW/MHz and 99. 98% precision and the circuit operates to 0. 38V supply voltage.

Nowadays, Access Control becomes the main challenges of many cloud services such as file sharing. In this article we propose a Blockchain based access control framework using access polynomial. Particularly, access control is implemented as a smart contract between data owner and user. Data owner encrypts the file with cipher-key and store it into the cloud storage. The cipher-key is embedded into a polynomial, namely access polynomial, which is retrievable by the end-users via user-key. The user-key is encrypted using ABE scheme and securely transmitted to end-user. Both user’ s request and data owner response are registered as Blockchain transactions which provide non-reputation logs. This method simply supports user’ s revocation by updating the access polynomial. The implementation results shows that our scheme has an acceptable performance over 20000 users. This scheme is decentralized and fault tolerant. Trusted Authority is responsible for issuing attributes to the users. Smart Contract is also lightweight Component and interface for sending Transactions to Blockcahin.

In this paper, a thin layer silicon solar cell device including metallic nanostructures is designed and studied to improving the performance and absorption of cellular light. First, a flat solar cell structure was studied and a light absorption spectrum was obtained for it. Then spherical nanoparticles and metallic silver nanostructures were embedded in the absorbent layer of the solar cell. The results show that the presence of nanostructures causes the collision of light in the designed solar cells to be concentrated. In this case, optical resonance increases due to the interaction of light input with metal nanoscale structures and causes light to propagate on a common metal and semiconducting surface, which is the same phenomenon of localized polariton plasmon. Simulation results that done with three dimensional finite difference time domain (FDTD) method, show a cellular efficiency of about 35%, Jsc is approximately 36. 2 mA/cm2 and fill factor is about 42. 6%.

A fully-integrated self-start-up low-voltage battery-less switched-capacitor step-up voltage converter is proposed that can operate in sub-threshold voltages. For this purpose, a two-branch charge pump is designed with cross-coupled voltage doubler structure. For proper operation, an anti-phase clock generator circuit is designed to operate at the same supply voltage. Body biasing technique is applied to the MOSFET transistors so that the circuit can operate in sub-threshold voltages. The proposed interleaved regulation technique improve the output voltage and current ripple, as well as the load regulation and transient response. The four-stage two-cell interleave charge pump circuit provide the output voltage of 1. 43 and 1. 95V under 300 and 400mV supply voltage with the pumping efficiency of 96. 3% and 97. 2%, and CP power efficiency of 93. 3% and 95. 1%, respectively. Post-layout simulation in 0. 18µ m CMOS technology shows a 24µ s ramp-up time and 0. 24% output voltage ripple at 20MHz switching frequency and 1pF load capacitance. The chip area of the proposed circuit is 0. 012mm2 while the CP consuming only 21. 4nW.

In the investigation presented with a focus on the applicability of adaptive control based on neural network to nonlinear systems in the presence of uncertainties, an adaptive control in association with intelligent tools with the key goal of adjusting nonlinear system’ s parameters under control is designed. For having a novel idea in this area, at first, an exact consideration is made in one such case concerning the similar works that have all provided to deal with the similar systems under control and then the proposed control approach is designed based on the neural networks. Using Lyapunov theory, adaptive laws suitable for the convergence of the closed loop system is provided. Using this theory, it is proved that all signals in the closed loop system are bounded and the error signal converges to zero as asymptotically. At the end, the results of simulation programs via MATLAB verifies the effectiveness of the control approach proposed.

In this paper, a high-bandwidth low-noise amplifier using gm-Boosting technique and noise cancellation method is presented. In this design, the common gate and input auxiliary amplifier are used in the input stage as the gm-Boosting, and the second stage is used to improve the gain and eliminate noise. This amplifier is designed with a 0. 18μ m CMOS technology, simulation results illustrate the voltage gain of 17. 5 ± 1. 5 dB at 2. 2 to 12. 2 GHz bandwidth, s11.

In this paper, a multipurpose nanowire transistor for the implementation of logical gates of NOT, NAND, and NOR is designed. In this design, a silicon nanowire with (7nm×7nm) area surrounded by silicon dioxide is used and there are three separated gates on that oxide. A simulation method is based on solving self-consistent Schrodinger-Poisson equations. The type of logical function can be specified by the control gate voltage level without any changes in the hardware and circuit structure. By using this simulation method, the electric potential of channel, carrier densities, and electric current are calculated. The effects of each gate on the electric characteristics of the device are analyzed and investigated. The optimum value of channel impurity concentration is obtained for the logical function characteristics to be symmetrical. In addition, the noise margins are calculated. The results indicate that the designed transistor can lead to the development of future integrated circuits.

In this paper, the performance of Cadmium Telluride (CdTe) solar cells, which are second generation or thin film solar cells, has been simulated using SCAPS software. The purpose of this paper is to improve the efficiency of the CdTe solar cell. The primary structure of the solar cell consists of Ni, CdTe, CdS, and n-ZnO-Al layers. Therefore, adding a thin layer of tin (SnS) of 0. 4 μ m to the absorbing layer (CdTe) leads to the creation of a backscattering or an auxiliary electrical field in the direction of the main field, between the adsorbent layer and the buffer layer (CdS). Therefore, adding the layer reduces the recombination of carriers at longer wavelengths by the auxiliary field, and leads to an improvement in the primary structure of the cadmium-telluride solar cell from the values of η =19. 09 %, FF= 85. 14%, JCS= 25. 77 mA/cm2, VOC = 0. 87 V to η =22. 98 %, FF= 85. 99%, JCS= 32. 51 mA/Cm2, VOC = 0. 82 V.

Energy consumption is a significant factor in wireless sensor networks (WSNs) which are consists of so many tiny and battery-based sensors. These sensors are distributed in different environments to perform distinct duties and whenever they consume the whole energy of their batteries, some parts of the necessary data of the network or its efficiency can be missed. Recently, in order to enhance these networks, extra energy extraction nodes which can harvest the energy from the environment, are used between sensors and the base station. Due to the high cost of energy harvesting nodes, minimizing the number of these nodes without affecting the quality of the signals is an important aspect of the wireless sensor network design. Therefore, the challenge is determining the efficient number of energy harvest nodes and their coordinates. In this work, for the first time, the Imperialist Competitive Algorithm (ICA) as one of the most advanced evolutionary algorithms is used to determine the minimum number of the energy harvest node. Based on the ICA’ s results, the K-Means algorithm is applied to clustering nodes. The simulation results show that the suggested method can improve the performance of the WSN by increasing its lifetime.

The general model for hardware accelerators and stream processors in the area of video, image or audio processing is comprised of two major parts of very large array of shift registers and arithmetic elements. A common example of digital signal processing units that fit the general model of data stream processors is the DA-based FIR, which uses add and shifts to perform multiply operations instead of high-cost multipliers. The shift registers are the major dynamic power consumer of data stream processors and FIR Filters, thus reducing the power consumption of the storage elements can contribute to energy efficiency of the whole system. On the other hand, the study of statistical properties can play an important role in the design and improvement of basic circuit parameters such as power consumption and efficiency. For example, transition density (TD) is one of the main parameters in dynamic (or switching) power consumption. By examining the TDs at the inputs of the data stream processors; where the data is a set of images selected from a database, it is shown that the TDs are less than 0. 5 in 55% of the inputs. Due to the sparsity of the evaluated signals, a low-power flip flop is designed in 65nm technology by applying clock-gating and multi-vdd methods, which is suitable for use in shift registers. Simultaneous use of two methods of clock-gating and multi-vdd in the 8×5 shift register array can achieve an improvement between 26 to 86% in dynamic and 84% improvement in static power consumption.