With the development of the electronic industry and the advent of modern processors, the attack model in the ALGORITHMs and ENCRYPTION protocols also changed. In spite of computational complexity in ALGORITHMs and cryptographic protocols, implementations can be a factor for the leakage of confidential information. The attacker can attack when electronic components are executing the ENCRYPTION operators using the secret key on sensitive data. As a result of computing, there is a leak of information in electronic components where attacks are called side-channel attacks. one of the most important sources of information leakage of side channels is time changes due to the execution of computation. The accesses to memory and the presence of branches in the program are expensive at runtime, so the processors use cache memory and branch-prediction to reduce this cost. Unfortunately, this optimization during execution leads to time changes in the execution of a program. The cache in the time side-channel attacks is more challenging and more practical. In this paper, we will review a variety of memory attacks on the implementation of the AES cipher ALGORITHM. by implementing the attacks and comparing the results, we will extract and compare the security weaknesses of implementing the AES cipher ALGORITHM against cache attacks.

Side-channel attacks are considered to be the most important problems of modern digital security systems. Today, Differential Power Attack (DPA) is one of the most powerful tools for attacking hardware ENCRYPTION ALGORITHMs in order to discover the correct key of the system. In this work, a new scheme based on randomizing power consumption of a fixed-operation logic gate is proposed. The goal of this method is enhancing the immunity of AES ALGORITHM against DPA. Having a novel topology to randomize the power consumption of each Exclusive-NOR gate, the proposed circuit causes random changes in the overall power consumption of the steps of the ALGORITHM; thus, the correlation between the instantaneous power consumption and the correct key is decreased and the immunity of the AES implementations which the key is injected into their process through Exclusive-NOR gates is extremely increased. The proposed method can be used as a general hardening method in the majority of cryptographic ALGORITHMs. The results of theoretical analysis and simulations in 90-nm technology demonstrate the capability of the proposed circuits to strengthen AES against DPA. The CMOS area and power consumption overhead is less than 1%.

Advanced ENCRYPTION Standard (AES) is one of the most common standard ENCRYPTION ALGORITHMs. Inspired by its characteristics, AES ALGORITHM can be implemented on various hardware platforms such as FPGA. Also, the data path can be implemented in either loop-unrolling or rolling architecture. These two architectures have direct impact on the amount of area consumption on the chip as well as system throughput. Then, a smart design should be able to consider the trade-off between area and throughput and provide a good balance between these two conflicting factors. In this paper, we propose such a design to represent the area-throughput trade-off for FPGA implementation of the AES ALGORITHM. With loop unrolling and pipelining techniques, throughput of 71.35 Gbps is achievable in Virtex 7 FPGA (xc7v585t-3ff1157). This design has just used 3669 Slices on the chip. The extracted results from the Place & Route report of Xilinx ISE 14.2 indicates that the maximum attainable clock frequency is 570.776 MHz.

This paper describes the implementation of a low power and high-speed ENCRYPTION ALGORITHM with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key ENCRYPTION ALGORITHM AES (Advanced ENCRYPTION Standard), in order to decrease the power using retiming and glitch and operand isolation techniques in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Such procedure makes AES suitable for fast image ENCRYPTION.Implementation of a 128-bit AES on FPGA of Altera Company has been done, and the results are as follows: throughput, 6.5 Gbps in 441.5 MHz and 130mw power consumption. The time of encrypting in tested image with 32*32 sizes is 1.25ms.

The A5/1 ALGORITHM is one of the most famous stream cipher ALGORITHMs used for over-the-air communication privacy in GSM. The purpose of this paper is to analyze several weaknesses of A5/1, including an improvement to an attack and investigation of the A5/1 state transition. Biham and Dunkelman proposed an attack on A5/1 with a time and data complexity of 239.91and 221.1, respectively.In this paper, we propose a method for identification and elimination of useless states from the pre-computed tables and a new approach to access the table in the online phase of the attack which reduces the time complexity to 237.89 and the required memory in half. Furthermore, we discuss another weakness of A5/1 by investigating its internal state transition and its keystream sequence period. Consequently, the internal states are divided into two classes, initially periodic and ultimately periodic. The presented model is verified using a variety of simulations which are consistent with the theoretical results.

A new image ENCRYPTION scheme using the advanced ENCRYPTION standard (AES), a chaotic map, a genetic operator, and a fuzzy inference system is proposed in this paper. In this work, plain images were used as input, and the required security level was achieved. Security criteria were computed after running a proposed ENCRYPTION process. Then an adaptive fuzzy system decided whether to repeat the ENCRYPTION process, terminate it, or run the next stage based on the achieved results and user demand. The SHA-512 hash function was employed to increase key sensitivity. Security analysis was conducted to evaluate the security of the proposed scheme, which showed it had high security and all the criteria necessary for a good and efficient ENCRYPTION ALGORITHM were met. Simulation results and the comparison of similar works showed the proposed encryptor had a pseudo-noise output and was strongly dependent upon the changing key and plain image.

In this paper, a new structure for image ENCRYPTION using recursive cellular automata is presented. The image ENCRYPTION contains three recursive cellular automata in three steps, individually. At the first step, the image is blocked and the pixels are substituted by reversible cellular automata. In the next step, pixels are scrambled by the second cellular automata and at the last step, the blocks are attached together and the pixels are substituted by the third cellular automata. Due to reversibility of cellular automata, the decryption of the image is possible by doing the steps reversely. The experimental results show that encrypted image is not understandable visually, also this ALGORITHM has satisfactory performance of quantitative assessment from some other schemes.

This paper mainly focused on implementation of AES ENCRYPTION and decryption standard AES-128. All the transformations of both ENCRYPTION and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. This method can make it a very low-complex architecture, especially in saving the hardware resource in implementing the AES InverseSub Bytes module and Inverse Mix columns module. As the S -box is implemented by look-up-table in this design, the chip area and power can still be optimized. The new Mix Column transformation improves the performance of the inverse cipher and also reduces the complexity of the system that supports the inverse cipher. As a result this transformation has relatively low relevant diffusion power. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.

The International Data ENCRYPTION ALGORITHM (IDEA)is a symmetric block Cipher with 64 block size and a 128-bit secret key. This ALGORITHM maps a 64-bits plaintext into 64-bits ciphertext in 8. 5 ENCRYPTION rounds. This ALGORITHM has so far been resistant against most known attacks. In this paper, the resistance of IDEA ALGORITHM against correlation power side channel attack is evaluated. By implementing this ALGORITHM on PIC micro controller platform, several samples of power consumption were measured during processing. The results of analyzing the measured samples indicate the resistance of the ALGORITHM to the correlation power side channel analysis.