REDUCING OFF-STATE CURRENT IN NANO-SCALE DOUBLE GATE JUNCTIONLESS FIELD EFFECT TRANSISTOR (DGJL-FET) USING DOPING ENGINEERING OF CHANNEL REGION

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KALANTARI S.; VADIZADEH M.

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Paper Information

Journal: NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ Year:2018 | Volume:16 | Issue:1 Page(s): 37-42

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Title

REDUCING OFF-STATE CURRENT IN NANO-SCALE DOUBLE GATE JUNCTIONLESS FIELD EFFECT TRANSISTOR (DGJL-FET) USING DOPING ENGINEERING OF CHANNEL REGION

Author(s)

KALANTARI S. | VADIZADEH M. | Issue Writer Certificate

Keywords

DOUBLE-GATE JUNCTIONLESS FIELD EFFECT TRANSISTOR (DGJL-FET)Q1

GATE DELAYQ1

SUB-THRESHOLD SLOPEQ1

DOPING ENGINEERINGQ1

IOFF/ION RATIOQ1

Abstract

Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current in DGJL-FET, which is called modified DGJL-FET. In this structure, the channel doping under the gate is the same as the drain and source doping but higher than the mid-channel doping. The simulation results indicated that reducing the thickness of the doped layer under the gate, D, resulted in the reduced OFF-state current. For the proposed device with 10 nm channel length, the OFF-state current is less than that in the regular DGJL-FET by two orders of magnitude. Performance of the regular DGJL-FET and modified DGL-FET for different channel lengths is compared based on the IOFF/ION RATIO, SUB-THRESHOLD SLOPE (SS), and intrinsic GATE DELAY. For modified DGJL-FET, the mid-channel doping and Dare considered as additional parameters for improving the device’s performance in nanometer regime. The simulation results indicated that in the proposed device with channel length of 15 nm, values of SS and IOFF/ION RATIO are improved compared to the regular DGJL-FET by 14% and 106 orders of magnitude, respectively.

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References

IMPROVING GATE DELAY AND ION/IOFF HETROSTRUCTURE FIELD EFFECT DIODE (H-FED) BY USING HEAVY DOPED LAYERS IN THE CHANNEL

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APA: Copy

KALANTARI, S., & VADIZADEH, M.. (2018). REDUCING OFF-STATE CURRENT IN NANO-SCALE DOUBLE GATE JUNCTIONLESS FIELD EFFECT TRANSISTOR (DGJL-FET) USING DOPING ENGINEERING OF CHANNEL REGION. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ, 16(1 ), 37-42. SID. https://sid.ir/paper/228082/en

Vancouver: Copy

KALANTARI S., VADIZADEH M.. REDUCING OFF-STATE CURRENT IN NANO-SCALE DOUBLE GATE JUNCTIONLESS FIELD EFFECT TRANSISTOR (DGJL-FET) USING DOPING ENGINEERING OF CHANNEL REGION. NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ[Internet]. 2018;16(1 ):37-42. Available from: https://sid.ir/paper/228082/en

IEEE: Copy

S. KALANTARI, and M. VADIZADEH, “REDUCING OFF-STATE CURRENT IN NANO-SCALE DOUBLE GATE JUNCTIONLESS FIELD EFFECT TRANSISTOR (DGJL-FET) USING DOPING ENGINEERING OF CHANNEL REGION,” NASHRIYYAH -I MUHANDISI -I BARQ VA MUHANDISI -I KAMPYUTAR -I IRAN, A- MUHANDISI -I BARQ, vol. 16, no. 1 , pp. 37–42, 2018, [Online]. Available: https://sid.ir/paper/228082/en

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