HARDWARE DESIGN OF THE DES ENCRYPTION AND DECRYPTION SYSTEMS USING VHDL TOOLS

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SHERAFAT A.R.; MAHZAB M.

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Journal: Year:2000 | Volume:34 | Issue:1 (67) Page(s): 25-40

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Title

HARDWARE DESIGN OF THE DES ENCRYPTION AND DECRYPTION SYSTEMS USING VHDL TOOLS

Author(s)

SHERAFAT A.R. | MAHZAB M. | Issue Writer Certificate

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Abstract

This paper presents the hardware design of the DES encryption and decryption systems and try to verify their performances. The hardware uses a clock rate of 20 MHz to encrypt an 80 Mbps input stream. This is twice as fast compared to existing hardware. The system was designed and its performance was Verified using VHDL standard tools. The advantages of using VHDL are that it simplifies the design and verification procedures, and enables one to implement the system into a single integrated circuit.

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APA: Copy

SHERAFAT, A.R., & MAHZAB, M.. (2000). HARDWARE DESIGN OF THE DES ENCRYPTION AND DECRYPTION SYSTEMS USING VHDL TOOLS. JOURNAL OF FACULTY OF ENGINEERING (UNIVERSITY OF TEHRAN), 34(1 (67)), 25-40. SID. https://sid.ir/paper/384784/en

Vancouver: Copy

SHERAFAT A.R., MAHZAB M.. HARDWARE DESIGN OF THE DES ENCRYPTION AND DECRYPTION SYSTEMS USING VHDL TOOLS. JOURNAL OF FACULTY OF ENGINEERING (UNIVERSITY OF TEHRAN)[Internet]. 2000;34(1 (67)):25-40. Available from: https://sid.ir/paper/384784/en

IEEE: Copy

A.R. SHERAFAT, and M. MAHZAB, “HARDWARE DESIGN OF THE DES ENCRYPTION AND DECRYPTION SYSTEMS USING VHDL TOOLS,” JOURNAL OF FACULTY OF ENGINEERING (UNIVERSITY OF TEHRAN), vol. 34, no. 1 (67), pp. 25–40, 2000, [Online]. Available: https://sid.ir/paper/384784/en

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