A TRANSISTOR-LEVEL PLACEMENT TOOL FOR ASYNCHRONOUS CIRCUITS

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SALEHI M.; PEDRAM H.; Saheb Zamani m.; NADERI M.; ARAGHI N.

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Seminar Paper

Paper Information

Seminar: CONFRANCE SALANE ANJOMANE COMPUTER IRAN
Year:2004 | Issue:9

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Title

A TRANSISTOR-LEVEL PLACEMENT TOOL FOR ASYNCHRONOUS CIRCUITS

Author(s)

SALEHI M. | PEDRAM H. | Saheb Zamani m. | NADERI M. | ARAGHI N.

Keywords

ASYNCHRONOUS CIRCUIT

PHYSICAL DESIGN

PLACEMENT AND ISOCHRONIC FORK

Abstract

ALTHOUGH ASYNCHRONOUS CIRCUITS ARE ACCEPTED AS LOW-POWER, LOW-EMI AND HIGH-PERFORMANCE CIRCUITS, THE ROADBLOCK TO WIDE ACCEPTANCE OF ASYNCHRONOUS DESIGN METHODOLOGY IS POOR CAD SUPPORT, ESPECIALLY PHYSICAL DESIGN TOOL. THERE ARE FEW ACADEMIC DESIGN TOOLS FOR ASYNCHRONOUS CIRCUIT DESIGN AND SYNTHESIS, BUT THERE IS NEITHER A PUBLISHED TOOL NOR A PUBLISHED DOCUMENT ON PHYSICAL DESIGN OF THESE CIRCUITS. SINCE THERE ARE NONCOMPLEMENTARY CMOS CIRCUITS IN THE NETLIST SYNTHESIZED USING CALTECH SYNTHESIS METHOD, THE COMMERCIAL CELL-BASED PLACEMENT TOOLS CAN’T BE USED. IN THIS PAPER WE HAVE PRESENTED A DESIGN FLOW FOR PLACEMENT OF ASYNCHRONOUS CIRCUITS AT TRANSISTOR-LEVEL CONSIDERING THEIR TIMING CONSTRAINTS.

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APA: Copy

SALEHI, M., PEDRAM, H., Saheb Zamani, m., NADERI, M., & ARAGHI, N.. (2004). A TRANSISTOR-LEVEL PLACEMENT TOOL FOR ASYNCHRONOUS CIRCUITS. Confrance Salane Anjomane Computer Iran. SID. https://sid.ir/paper/905583/en

Vancouver: Copy

SALEHI M., PEDRAM H., Saheb Zamani m., NADERI M., ARAGHI N.. A TRANSISTOR-LEVEL PLACEMENT TOOL FOR ASYNCHRONOUS CIRCUITS. 2004. Available from: https://sid.ir/paper/905583/en

IEEE: Copy

M. SALEHI, H. PEDRAM, m. Saheb Zamani, M. NADERI, and N. ARAGHI, “A TRANSISTOR-LEVEL PLACEMENT TOOL FOR ASYNCHRONOUS CIRCUITS,” presented at the Confrance Salane Anjomane Computer Iran. 2004, [Online]. Available: https://sid.ir/paper/905583/en

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