DESIGN OF ERROR DETECTING SERIAL MULTIPLIERS IN REVERSIBLE LOGIC

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ESLAMI F.; VALINATAYEJ M.; JAZAYERI H.

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Journal: ELECTRONIC INDUSTRIES Year:2017 | Volume:8 | Issue:1 Page(s): 99-110

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Information Journal Paper

Title

DESIGN OF ERROR DETECTING SERIAL MULTIPLIERS IN REVERSIBLE LOGIC

Author(s)

ESLAMI F. | VALINATAYEJ M. | JAZAYERI H. | Issue Writer Certificate

Keywords

BOOTH’S ALGORITHMQ2

SERIAL MULTIPLIERQ1

ERROR DETECTIONQ1

PARITY PRESERVINGQ2

FAULT TOLERANCEQ1

REVERSIBLE LOGICQ1

Abstract

Power consumption is one of the most challenging issues in design of electronic circuits. REVERSIBLE LOGIC is a solution for power optimization. In this paper, we propose three fault-tolerant SERIAL MULTIPLIER designs based on the REVERSIBLE LOGIC with ERROR DETECTION capability. The first proposed SERIAL MULTIPLIER which is based on the BOOTH’S ALGORITHM utilizes a new arrangement of reversible gates. The second proposed SERIAL MULTIPLIER for signed numbers is based on a newer algorithm called the K algorithm. This algorithm requires less cost compared to the Booth's algorithm.The third proposed fault-tolerant SERIAL MULTIPLIER which is optimized for unsigned number multiplication is based on the conventional Add & Shift method. The comparative results show that the proposed multipliers are much better than the existing designs considering the main criterions used in REVERSIBLE LOGIC circuits which include quantum cost, number of gates, number of garbage outputs, delay, and computational complexity.

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APA: Copy

ESLAMI, F., VALINATAYEJ, M., & JAZAYERI, H.. (2017). DESIGN OF ERROR DETECTING SERIAL MULTIPLIERS IN REVERSIBLE LOGIC. ELECTRONIC INDUSTRIES, 8(1 ), 99-110. SID. https://sid.ir/paper/229635/en

Vancouver: Copy

ESLAMI F., VALINATAYEJ M., JAZAYERI H.. DESIGN OF ERROR DETECTING SERIAL MULTIPLIERS IN REVERSIBLE LOGIC. ELECTRONIC INDUSTRIES[Internet]. 2017;8(1 ):99-110. Available from: https://sid.ir/paper/229635/en

IEEE: Copy

F. ESLAMI, M. VALINATAYEJ, and H. JAZAYERI, “DESIGN OF ERROR DETECTING SERIAL MULTIPLIERS IN REVERSIBLE LOGIC,” ELECTRONIC INDUSTRIES, vol. 8, no. 1 , pp. 99–110, 2017, [Online]. Available: https://sid.ir/paper/229635/en

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